A sub-1nm chip is a roadmap, not a part.

On 25 June, IBM said it had built the first working logic below the 1nm line, a 0.7nm node it calls NanoStack, with close to 100 billion transistors on a chip the size of a fingernail. That is roughly twice the density of the 2nm part IBM showed in 2021. The claim is a three-dimensional nanostack architecture, stacking the transistor structures rather than only shrinking them flat, and the projected gains are large: up to half again the performance, or seventy per cent better energy efficiency, against the 2nm node, plus the first meaningful jump in SRAM density in over a decade.

It is genuinely good news, and the right kind. Plenty of people have spent the last few years saying the shrink was over. This says the road runs on for another decade. The trap is reading a research demo as a shopping list.

A milestone is not a part

The gap between this announcement and a chip you can buy is the whole story. IBM showed 2nm in 2021, and it is only now approaching volume production, about five years later. A demonstration proves the physics is open. It does not give you yield, it does not give you a supply you can plan around, and it does not give you a price. NanoStack is a statement that the angstrom era is reachable, not a date you can put in a system spec.

This is the same pattern under every silicon headline. The number on the slide is the best case in a lab. The thing you actually build on is two or three years behind it, at a yield the foundry will commit to, in volumes you can secure.

The studio read

We build systems that have to run on hardware that exists, that we can source, and that a client can still buy a spare of in three years. So a sub-1nm milestone changes nothing we are specifying this quarter. What it does change is the shape of the bet you are making on the longer-lived work, the installation meant to run for years, the operational system with a hardware refresh budget.

• 01Specify for the part you can order today, not the one on the roadmap. The roadmap slips, the order does not.
• 02Design the compute as a thing you can swap. If the work assumes a fixed board forever, a better chip in two years is a rebuild, not an upgrade.
• 03Treat efficiency claims as the headline they are. Seventy per cent better efficiency at the same work is the gain that actually reaches a device budget, a thermal envelope, a battery, an always-on installation, far more often than raw speed does.
• 04Watch SRAM, not just the node name. On-chip memory has barely scaled for a decade, and for a lot of real workloads it is the bottleneck the marketing number hides.

The useful posture is neither breathless nor dismissive. The shrink continuing is good for everyone who ships on silicon, us included. But the discipline is to keep building for the parts on the shelf while reading the roadmap for where to leave room. The press release is for the decade. The purchase order is for this year, and those are not the same document.